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CY25562
Spread Spectrum Clock Generator
Features

Applications

50 to 200 MHz Operating Frequency Range Wide range of spread selections: 9 Accepts Clock and Crystal Inputs Low Power Dissipation 70 mW Typ (Fin = 65 MHz) Frequency Spread Disable Function Center Spread Modulation Low Cycle-to-cycle Jitter 8-pin SOIC Package
High resolution VGA controllers LCD panels and monitors Workstations and servers
Benefits

Peak EMI reduction by 8 to 16 dB Fast time to market Cost reduction
Logic Block Diagram
300K
Xin/ CLK
1
REFERENCE DIVIDER
PD
CP
Loop Filter
Xout
8
MODULATION CONTROL
FEEDBACK DIVIDER
vco
VDD
2
INPUT DECODER LOGIC
VDD VDD
DIVIDER & MUX
4 SSCLK
VSS
3
20 K
20 K
20 K
VSS
20 K
VSS
5 SSCC
6 S1
7 S0
Cypress Semiconductor Corporation Document Number: 38-07392 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 15, 2008
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CY25562
Pinout
Figure 1. Pin Configuration
XIN/CLK 1 VDD 2 8 XOUT 7 S0
CY25562
VSS 3 SSCLK 4 6 S1 5 SSCC
Pin Description
Pin # 1 2 3 4 5 6 Pin Name Xin/CLK VDD GND SSCLK SSCC S1 Type I P P O I I Positive power supply Power supply ground SSCG modulated clock output Spread spectrum clock control (enable/disable) function. SSCG function is enabled when input is high and disabled when input is low. This pin is pulled high internally. Tri-level logic input control pin used to select frequency and bandwidth. Frequency/bandwidth selection and tri-level logic programming. See Figure 2. Pin 6 has internal resistor divider network to VDD and VSS. Refer to Logic Block Diagram on page 1. Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth selection and tri-level logic programming. See Figure 2. Pin 7 has internal resistor divider network to VDD and VSS. Refer to Logic Block Diagram on page 1. Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock drives Xin/CLK. Pin Description Clock or crystal connection input. Refer to Table 1 for input frequency range selection.
7
S0
I
8
Xout
O
General Description
CY25562 is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic interference (EMI) found in today's high speed digital electronic systems. CY25562 uses a Cypress proprietary Phase Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading system performance. CY25562 is a very simple and versatile device to use. The frequency and spread percentage range is selected by programming S0 and S1 digital inputs. These inputs use three logic states including high (H), low (L), and middle (M) logic levels to select one of the nine available spread percentage ranges. Refer to Table 1 for programming details. CY25562 is intended for applications with a reference frequency in the range of 50 to 200 MHz. A wide range of digitally selectable spread percentages is made possible by using tri-level (high, low, and middle) logic at the S0 and S1 digital control inputs. The output spread (frequency modulation) is symmetrically centered on the input frequency. Spread spectrum clock control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing. CY25562 is available in an eight-pin SOIC package with a 0 to 70C operating temperature range. Refer to CY25561 for applications with lower drive requirements, and CY25560 with lower drive and frequency requirements.
Document Number: 38-07392 Rev. *C
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CY25562
Table 1. Frequency and Spread Percentage Selection (Center Spread)
5 0 - 1 0 0 M H z (L o w R a n g e ) In p u t F re q u e n c y (M H z ) 50 - 60 60 - 70 70 - 80 80 - 100 S1=M S0=M (% ) 4 .3 4 .0 3 .8 3 .5 S1=M S0=0 (% ) 3 .9 3 .6 3 .4 3 .1 S1=1 S0=0 (% ) 3 .3 3 .1 2 .9 2 .7 S1=0 S0=0 (% ) 2 .9 2 .6 2 .5 2 .2 S1=0 S0=M (% ) 2 .7 2 .5 2 .4 2 .1
S e le c t th e F req u e n c y a n d C e n te r S p re a d % d e s ire d a n d th e n set S1, S0 as in d ic a te d .
1 0 0 - 2 0 0 M H z (H ig h R a n g e ) In p u t F re q u e n c y (M H z ) 100 - 120 1 2 0 -1 3 0 130 - 140 140 - 150 150 - 160 160 - 170 170 - 180 180 - 190 190 - 200 S1=1 S0=M (% ) 3 .0 2 .7 2 .6 2 .6 2 .5 2 .4 2 .4 2 .3 2 .3 S1=0 S0=1 (% ) 2 .4 2 .1 2 .0 2 .0 1 .8 1 .8 1 .8 1 .7 1 .6 S1=1 S0=1 (% ) 1 .6 1 .4 1 .3 1 .3 1 .2 1 .2 1 .2 1 .1 1 .1 S1=M S0=1 (% ) 1 .3 1 .1 1 .1 1 .1 1 .0 1 .0 1 .0 0 .9 0 .9
S e le c t th e F req u e n c y a n d C e n te r S p re a d % d e s ire d a n d th e n set S1, S0 as in d ic a te d .
Tri-level Logic
With binary logic, four states can be programmed with two control lines, whereas tri-level logic can program nine logic states using two control lines. Tri-level logic in CY25562 is implemented by defining a third logic state in addition to the standard logic "1" and "0." Pins six and seven of CY25562 recognize a logic state by the voltage applied to the respective pin. These states are defined as "0" (low), "M" (middle), and "1" (one). Each of these states have a defined voltage range that is interpreted by CY25562 as "0", "M," or "1" logic state. Refer to Table 2 for voltage ranges for each logic state. CY25562 has two equal value resistors connected internally to pin 6 and pin 7, which produce the default "M" state. Pins six and/or seven can be tied directly to ground or VDD to program a logic "0" or "1" state, respectively. See the following examples: Figure 2. Tri-level Logic Example
VDD VDD
CY25562
S0 = "M" (N/C) 7 S0
CY25562
S0 = "1" S1 S1 = "0" (GND) VDD 6 VDD SSCC = "1" 5 7 S0
CY25562
S0 = "1" 7 S0
S1 = "0" (GND)
6
S1 S1 = "1" 6
S1
SSCC = "1"
5
SSCC = "1"
5
SSCG Theory of Operation
CY25562 is a PLL-type clock generator using a proprietary Cypress design to modulate the reference clock. By precisely controlling the bandwidth of the output clock, CY25562 becomes a low-EMI clock generator. The theory and detailed operation of CY25562 is discussed in the following sections.
EMI
All digital clocks generate unwanted energy in their harmonics. Conventional digital clocks are square waves with a duty cycle that is very close to 50 percent. Because of this 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd
harmonics, that is; third, fifth, seventh, etc. The amount of energy contained in the fundamental and odd harmonics can be reduced by increasing the bandwidth of the fundamental clock frequency. Conventional digital clocks have a very high Q factor; all the energy at that frequency is concentrated in a very narrow bandwidth, and consequently, higher energy peaks. Regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. By reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test satisfies agency requirements for EMI. Conventional methods of reducing EMI use shielding, filtering, multi-layer PCBs, etc. CY25562 reduces the peak energy in the clock by increasing the clock bandwidth, thus lowering the Q.
Document Number: 38-07392 Rev. *C
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CY25562
SSCG
SSCG uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak and cycle-to-cycle. CY25562 takes a narrow band digital reference clock in the range of 50 to 200 MHz and produces a clock that sweeps between a controlled start (F1) and stop (F2) frequency at a precise rate of change. To understand what happens to a clock when SSCG is applied, consider a 200 MHz clock with a 50 percent duty cycle, as shown in this figure.
important factor in the amount of EMI reduction realized from an SSCG clock. The modulation domain analyzer is used to visualize the sweep waveform and sweep period. Figure 3 shows the modulation profile of a 200 MHz SSCG clock. Notice that the actual sweep waveform is not a simple sine or sawtooth waveform. Figure 3 also shows a scan of the same SSCG clock using a spectrum analyzer. The spectrum analyzer scan shows a 10 dB reduction in the peak RF energy when using CY25562 SSCG clock.
50 %
50 %
Modulation Rate
Spread spectrum clock generators use frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (Fmax) and minimum frequency of the clock (Fmin) determine this band of frequencies. The time required to transition from Fmin to Fmax and back to Fmin is the period of the modulation rate, Tmod. Modulation rates of SSCG clocks are generally referred to in terms of frequency or Fmod = 1/Tmod. The input clock frequency, Fin, and the internal divider count, Cdiv, determine the modulation rate. In some SSCG clock generators, the selected range determines the internal divider count. In other SSCG clocks, the internal divider count is fixed over the operating range of the part. CY25562 has a fixed divider count of 2332.
Tc = 5.0 ns
Clock frequency = fc = 200 MHz Clock period = Tc = 1/200 MHz If this clock is applied to the Xin/CLK pin of CY25562, the output clock at pin 4 (SSCLK) sweeps back and forth between two frequencies. These two frequencies, F1 and F2, calculate total amount of spread or bandwidth applied to the reference clock at pin 1. As the clock is making the transition, sweep, from F1 to F2, the amount of time and sweep waveform become a very
Figure 3. SSCG Clock, Part Number, Fin = 200 MHz
Device CY25562
Cdiv 2332
(All Ranges)
Example: Device = CY25562 Fin = 200 MHz Range = S1 = 1, S0 = 1 Then; Modulation Rate = Fmod = 200 MHz/2332 = 85.7 kHz.
Modulation Profile
Spectrum Analyzer
Document Number: 38-07392 Rev. *C
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CY25562
Part Number Application Schematic
Figure 4. Application Schematic
VDD
C3 0.1 uF
2 1
200 MHz Reference Clock
8
XIN/CLK
VDD SSCLK
4
XOUT
CY25562
5
S1 SSCC VSS
3
6
VDD
VDD
S0
7
The schematic in Figure 4 demonstrates how CY25562 is configured in a typical application. This application is using a 200 MHz reference clock connected to pin 1. Because an external reference clock is used, pin 8 (Xout) is left unconnected. This configuration depicts the profile and spectrum scans shown in Figure 3. Note that S0=S1=1, for a spread of approximately 1.1 percent.
Document Number: 38-07392 Rev. *C
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CY25562
Absolute Maximum Ratings[1, 2]
Supply voltage (VDD) ......................................-0.5V to +6.0V DC input voltage .................................... -0.5V to VDD + 0.5V Junction temperature.................................. -40C to +140C Operating temperature ....................................... 0C to 70C Storage temperature................................... -65C to +150C Static discharge voltage (ESD)............................ 2,000V Min
Table 2. Electrical Characteristics VDD = 3.3V, TA = 25C, and CL (Pin 4) = 15 pF unless otherwise noted Parameter VDD VINH VINM VINL VOH1 VOH2 VOL1 VOL2 Cin1 Cin2 Cin2 IDD1 IDD2 IDD3 Description Power supply range Input high voltage Input middle voltage Input low voltage Output high voltage Output high voltage Output low voltage Output low voltage Input capacitance Input capacitance Input capacitance Power supply current Power supply current Power supply current 10% S0 and S1 only S0 and S1 only S0 and S1 only IOH = 6 mA IOH = 20 mA IOH = 6 mA IOH = 20 mA Xin/CLK (pin 1) Xout (pin 8) S0, S1, SSCC (pins 7, 6, 5) Fin = 65 MHz, CL = 15 pF Fin = 200 MHz, CL =15 pF Fin = 200 MHz, no load 3 6 3 4 8 4 23 53 48 Conditions Min 2.97 0.85VDD 0.40VDD 0.0 2.4 2.0 0.4 1.2 5 10 5 30 66 60 Typ 3.3 VDD 0.50VDD 0.0 Max 3.63 VDD 0.60VDD 0.15VDD Unit V V V V V V V V pF pF pF mA mA mA
Table 3. Electrical Timing Characteristics VDD = 3.3V, TA = 25C, and CL = 15 pF unless otherwise noted. Rise/Fall at 0.4 to 2.4V, Duty at 1.5V Parameter ICLKFR tRISE tFALL tRISE tFALL DTYin DTYout FM1 FM2 CCJ1 CCJ2 CCJ3 Description Input clock frequency range Clock rise time (pin 4) Clock fall time (pin 4) Clock rise time (pin 4) Clock fall time (pin 4) Input clock duty cycle Output clock duty cycle Frequency modulation Frequency modulation Cycle-to-Cycle jitter Cycle-to-Cycle jitter Cycle-to-Cycle jitter Conditions Pk-Pk = 3.3 volts SSCLK, CL = 15 pF, 200 MHz SSCLK, CL = 15 pF, 200 MHz SSCLK, CL = 33 pF, 200 MHz SSCLK, CL = 33 pF, 200 MHz XIN/CLK (pin 1) SSCLK1 (pin 4) Fin = 70 MHz Fin = 200 MHz Fin = 50 MHz, mod ON Fin = 120 MHz, mod ON Fin = 200 MHz, mod ON Min 50 0.8 0.8 1.1 1.1 30 45 29.5 85.0 0.9 0.9 1.45 1.5 50 50 30.0 85.4 150 175 250 Typ Max 200 1.0 1.0 1.8 1.9 70 55 30.5 86 175 200 300 Unit MHz ns ns ns ns % % kHz kHz ps ps ps
Ordering Information
Part Number CY25562SXC CY25562SXCT Package Type 8-pin SOIC, Pb-free 8-pin SOIC - tape and reel, Pb-free Product Flow Commercial, 0 to 70C Commercial, 0 to 70C
Notes 1. Operation at any absolute maximum rating is not implied. 2. Single power supply: The voltage on any input or I/O pin cannot exceed the power pine during power-up.
Document Number: 38-07392 Rev. *C
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CY25562
Package Drawing and Dimensions
Figure 5. 8 Lead (150 Mil) SOIC-SO8
51-85066 *C
Document Number: 38-07392 Rev. *C
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CY25562
Document History Page
Document Title: CY25562 Spread Spectrum Clock Generator Document Number: 38-07392 Rev. ** *A *B *C ECN No. 115526 119444 122703 2567245 Submission Date 07/08/02 10/17/02 12/28/02 09/16/08 Orig. of Change OXC RGL RBI New Data Sheet Corrected the values in the Absolute Maximum Ratings to match the device. Added power up requirements to maximum ratings information. Description of Change
PYG/KVM/ Replaced CY25562SC w/ CY25562SXC, CY255652SCT w/ CY25562SXCT. AESA Package changed from S8 to SZ8. Updated template.
(c) Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07392 Rev. *C
Revised September 15, 2008
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